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The increasing trend of automotive electronics mandates the introduction of multiple processors in automotive electronics. The automotive electronic systems have to operate in harsh environments having a high temperature range, high humidity, unpredictable vibrations and rapid voltage variation. In such environment, the automotive electronic systems become vulnerable to intermittent and transient failures. Depending upon the importance of the tasks performed by the processor, a processor’s failure inside automotive electronic system may lead to serious consequences. Fault tolerant computing techniques are used to keep the computer systems running in spite of one or more processors’ failures. The concept of fault tolerant is well known in many applications such as airplanes, industry, and military. However, the question of fault tolerant design has drawn little attention in automotive electronics.

Automotive multiplexing allows sharing information among various intelligent modules inside an automotive electronic system. In order to achieve an optimum functionality, the information should be exchanged among various electronic modules in real time. New features are introduced in automobiles such as Intelligent Vehicle Highway System (IVHS), intelligent transportation support system, engine immobilizers, night vision assistance system, and automated collision avoidance and notification system. The inclusion of such features increases the data traffic over the multiplexing bus. Also, these features require very high speed and expensive bus. Data reduction techniques are used to send the data over a transmission media at high speed. Using the data reduction techniques, we will be able to include new features in automobiles without the need of a high speed bus. Since the automotive environment is different, a special data reduction algorithm is mandated.

Automotive electronics can be divided into subsystems according to their functions and physical locations Employing this concept, a hierarchical architecture of automotive electronics may be evolved In this paper a hierarchical fault tolerant distributed processing system has been introduced The system consists of a central controller (CC), m subsystems, a main bus and a shared memory module Each subsystem consists of n processors, one smart sensor group and one smart actuator group The central controller maintains the performance history of every processor in system In case of a processor's failure, the CC assigns the tasks of the faulty processor to another processor within the same subsystem Reliability, which is the probability of a correctly working system for an interval of time [t-t0], has been evaluated An algorithmic approach based on the truth table method has been developed for evaluating the reliability of the proposed hierarchical architecture A comparison of the reliability calculation has been done between the proposed architecture and a system without fault tolerance capability The results show that the proposed architecture provides better reliability

Distributed Computing systems consist of several processors that interact and cooperate with each other by message passing. These distributed systems provide many attractive features such as fault tolerance, resource sharing, high reliability and high throughput. These features make distributed systems good candidates for many real time applications such as aircraft, space crafts and automotive control. Car Industry is striving to provide reliable and cost effective Computing systems for their automobiles. As the number of processors increases in a vehicle, the demand increases to provide a reliable Computing system for the automotive. Therefore, it is important to develop specialized distributed Computing systems for this type of applications taking into consideration reliability as well as cost of the system. In this paper, a distributed Computing system architecture has been proposed for automotive applications.