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As a cost effective solution to making microcontroller based systems “J1850[1] aware”, a peripheral device (the HIP7010) was developed to extend the capabilities of standard microcontrollers. From the perspective of the Host, the peripheral device handles J1850 messages as a series of bytes (similar in concept to a universal asynchronous receiver/transmitter [UART]). The architecture of the HIP7010 is discussed. The design of the J1850 interface, state machine, status/control blocks, cyclical redundancy check (CRC) hardware, host interface, and fail-safe features are detailed. Illustrations are provided of: Host/HIP7010 interfacing; message transmission and reception; error handling; and In-Frame Response (IFR) generation.

A 6805 based microcontroller (HIP7030A2) was developed with integrated J1850[1] hardware. Trade-offs were made between hardware and software in terms of cost, speed, memory requirements, and processor overhead. The microcontroller has been used to construct J1850 compliant, single-byte and three-byte header, variable pulse width (VPW) nodes. Algorithms for symbol processing, cyclical redundancy check (CRC) generation/verification, and message filtering were developed which validate the suitability of the HIP7030A2 for stand-alone and dual-processor nodes. Firmware was developed which transforms the HIP7030A2 into a J1850 message coprocessor for single-byte header, VPW messages. Known as the Programmable Communications Interface (PCI) it serves as a slave device to host processors dramatically simplifying the task of J1850 enabling a module.