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Virtual system integration and testing using hardware-in-the-loop (HiL) simulation enables front-loading of development tasks, provides a safer and reliable testing environment and reduces prototype hardware costs. One of the greatest challenges to overcome when performing HiL simulations is assuring a high model accuracy under stringent real-time requirements with acceptable development effort. This article represents a novel solution by deriving the plant model for HiL directly from the existing detailed models from the component layout phase using co-simulation methodology. It provides an effective and efficient model implementation and validation process followed by detailed quantitative analysis of the test results referred to the engine test bench measurements.