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Design assurance guidance such as DO-254, and commercial off the shelf (COTS) increasing popularity in high critical mission have pushed the validation and verification methodologies to improve by integrating fault tolerance analysis in reliability assessment. A novel methodology for analysing the sensitivity of digital designs to single event upsets (SEU) is proposed. We first characterize basic combinational circuit models using fault injection via mutation technique at low level of abstraction. Error analysis is performed at primary outputs to identify patterns that are collected in a faulty behaviour library. This library is then used at a high level of abstraction to execute a sensitivity analysis on a digital design model. A reliability report is then generated showing the soft error rate (SER) and the benign errors count. We proved our methodology by analysing the radiation sensitivity of a discrete wavelet transform architecture using two different sets of data.