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The verification of Robustness is conceptually simple, once the reasonable set of “abnormal operating conditions” has been established. During testing those conditions are created and the FPGA/CEH response is noted. Depending upon system requirements, sometimes the FPGA/CEH response need not be “to work normally” but should at a minimum return to normal operation once normal conditions are reestablished. Part of the analysis is to establish acceptable FPGA/CEH responses to the “abnormal operating conditions”. Some of the acceptable responses may actually affect the LRU/CCA hardware performance or software functions hosted on the system, an early identification of such interdependence is essential for the planning of robustness testing. The test cases implementing robustness testing conform to the same constraints and pedigree as any requirements based test case. The key here is to know the scope of the tests and plan accordingly.