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This paper presents follow-on material and conclusions to a previously published paper that presented work to develop and validate life prediction models for SiC device packaging [ 1 ]. The first step in this work was to determine the most probable failure modes in the device packaging. After determining the expected dominant failure modes of a SiC semiconductor packaging, appropriate models were identified and applied to the packaging in order to track remaining useful life. Once failure modeling was completed, the life prediction models were validated. Validation consisted of accelerated life testing designed to stress specific parts of the device package so as to stimulate the desired failure mechanism. This paper will review the three testing methodologies designed to excite the three dominant failure mechanisms in the electronic packaging. These tests can be broken into two types of general tests: power cycling and high temperature reverse bias testing (HTRB).