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The topic of timing has already been recognized as a major challenge when designing safety-critical automotive architectures. Consequently the availability of appropriate performance and timing analysis methods is key to building reliable automotive electric and electronics (E/E) and software architectures. Due to the potential performance increase, power reduction and cost-efficiency multicore solutions for automotive real-time environments receive growing attention. But the prediction of the timing behavior for multicore electronic control unit (ECU) systems becomes more complicated. Even in setups with static task-to-processor mapping, the execution of the tasks is usually not independent. The use of the same physical hardware, such as memories, coprocessors, or network components, makes inter-core interference unavoidable and may introduce hard-to-find timing problems including missed deadlines that can finally make the entire system fail.